The surface area of a semiconductor chip can be roughly divided into two regions: an input/output (I/O) region and a core region. The I/O region includes cells which transfer data signals to and from the chip. These cells may be dedicated to receiving input data signals to the chip, supplying output data signals from the chip or selectively transferring both input and output data signals. The core region includes all other elements on the chip including logic elements, memory, etc. For ease of providing external connections to the I/O cells, the I/O region is typically located proximate the edge of the chip. Each I/O cell is provided with a pad to which a lead wire or pin can be bonded. In addition, the I/O cell can include transistors for driving or boosting the transferred signal and/or transistors for providing electrostatic discharge (ESD) protection and latch-up prevention for the chip.
Data which is input to a semiconductor chip includes both data that is required for normal operation of the chip (hereafter referred to as operational data) and data that is required for testing the chip (hereafter referred to as test data). A test procedure which uses test data is known as boundary scan testing. IEEE Standard 1149.1 describes a boundary scan test procedure for an integrated circuit. In boundary scan testing, a string of buffers are interconnected so as to form a shift register chain around the border of the core region. Data can be entered into these buffers through one or more chip input pins.
The boundary scan test data must be entered into the chip's core logic to test the chip. Basically, the test data must reach the same core logic elements as the operational data. Typically, a multiplexer is used to select operational or test data. In the past, such multiplexers have been included in the core logic with several undesirable results.
First, the multiplexer consumes valuable chip space. For high pin count chips requiring many multiplexers, the required space can be significant. In addition, because the input signal can be fairly strong, the multiplexer must be carefully designed to prevent "latch-up." Such designs require careful attention to the separation of p and n type dopant regions which can require even additional chip space.
Second, many multiplexer designs introduce a propagation delay from the input pad to core logic for the operational data. The propagation delay through the multiplexer may be in the order of 1.025 ns with an integrated circuit cell fabricated using 1 micron CMOS processes. While this delay may not be significant for many conventional low speed circuits, such a delay becomes critical in high speed, e.g., 50 megahertz systems.
Third, the location of the multiplexer should be near to the input cell to reduce propagation delays, capacitive loading, etc. However, it is not always possible to provide an optimal routing of conductive lines for the preferred location of the multiplexer.
Fourth, many conventional multiplexer designs require the data to be buffered after being transferred through the multiplexer in order to have sufficient signal strength to supply several core logic elements. The ability to simultaneously feed multiple elements from a single supply line is known as "fan out." The additional buffering required for large fan out designs introduces further propagation delays for operational data signals.